A new approach for enhancing the process-variation tolerance of digitalcircuits is described. We extend recent advances in statistical timing analysisinto an optimization framework. Our objective is to reduce the performancevariance of a technology-mapped circuit where delays across elements arerepresented by random variables which capture the manufacturing variations. Weintroduce the notion of statistical critical paths, which account for bothmeans and variances of performance variation. An optimization engine is used tosize gates with a goal of reducing the timing variance along the statisticalcritical paths. We apply a pair of nested statistical analysis methodsdeploying a slower more accurate approach for tracking statistical criticalpaths and a fast engine for evaluation of gate size assignments. We derive anew approximation for the max operation on random variables which is deployedfor the faster inner engine. Circuit optimization is carried out using again-based algorithm that terminates when constraints are satisfied or nofurther improvements can be made. We show optimization results that demonstratean average of 72% reduction in performance variation at the expense of average20% increase in design area.
展开▼
